A Nanochannel Fabrication Technique without Nanolithography

We have developed a new nanochannel fabrication technique using chemical-mechanical polishing (CMP) and thermal oxidation. With this technique, it is possible to control the width, length, and depth of the nanochannels without the need for nanolithography. The use of sacrificial SiO2 layers allows the fabrication of centimeter-long nanochannels. In addition, the fabrication process is CMOS compatible. We have successfully fabricated an array of extremely long and narrow nanochannels (i.e., 10 mm long, 25 nm wide, and 100 nm deep) with smooth inner surfaces. Introduction. Nanofabrication of extremely small fluidic structures provides powerful tools for the field of bionanotechnology.1-4 Nanochannels are essential components in nanofluidic systems. Among the many requirements for the nanochannel fabrication technique are the following: It should be cost-effective, able to precisely control channel dimensions, and be CMOS compatible for ultimate integration with microelectronics. Previously, various nanochannel fabrication techniques based either on e-beam lithography, step sidewalls, or laser machining have been reported.5-7 However, these techniques suffer from several limitations. For example, e-beam lithography-based processes are relatively expensive.5 The step sidewall approach has limitations in the maximum possible lengths of the nanochannel because of lateral sacrificial etching effects.6 Finally, laser machining can only produce nanochannels with minimum widths in the range of a few hundred nanometers and the fabrication process is not CMOS compatible.7 In this paper, we describe the demonstration of a cost-effective nanochannel fabrication technique with precisely controlled dimensions, using a conventional CMOS fabrication process. Experimental Section. Figure 1 shows the fabrication procedures. First, 100 nm thick amorphous silicon is deposited as shown in Figure 1a. The deposited amorphous silicon thickness determines the depth of the nanochannel. The photolithography is performed for determining the length and shape of the nanochannel. And it is etched using reactive ion etch (RIE) and subsequently oxidized in 1000 °C dry O2 for 40 min, as shown in Figure 1b. The SiO2 thickness is about 50 nm, which determines the width of the nanochannel. Thus, the width of the nanochannel is controlled by adjusting SiO2 film thickness with the oxidation temperature or time.8 The lower limit of the width in the nanochannel is about 5 nm, because the dry O2 oxidation can readily produce 5 nm SiO2 film. And 500 nm thick amorphous silicon is deposited as shown in Figure 1c. The overlayer thickness is approximately five times that of the amorphous silicon layer, to minimize “dishing” effects. CMP process is performed to expose the gap oxide as shown in Figure 1d. Then, the gap oxide is vertically etched in the (10:1) buffered oxide etch (BOE) for 20 min as shown in Figure 1e. The oxide in * Corresponding author. E-mail: [email protected]. Figure 1. Fabrication procedures. (a) SiNx and first amorphous Si deposition; (b) RIE and dry O2 oxidation for the nanometer gap; (c) second amorphous Si deposition; (d) CMP until the gap oxide is exposed. (e) The oxide in the nanometer gap is etched. (f) The Au or oxide layer is used for sealing. NANO LETTERS 2003 Vol. 3, No. 1